High Frequency Measurements Web Page
Douglas C. Smith

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Technical Tidbit - April 2003
Measurement and Interpretation of High Frequency Chip Noise

Loop on chip package for measurement
Figure 1. Square Loop Measurement of Chip Package Noise

Abstract: Voltage drops in chip packages can cause significant signal integrity and EMC problems. The good news is that in many cases these voltages can be measured through mutual inductance. Measured results and their interpretation are discussed.

Discussion: Figure 1 shows a square shielded (shielding is not necessary for this measurement) loop positioned over a chip. Its output (Mdi/dt) is proportional to the voltage drop (Ldi/dt) across bonding wires and the lead frame of the chip package. In general, the loop output is a small fraction of the voltage drop in the package, about 25% in many cases. A detailed description of a method using the loop's output to diagnose chip package problems is given in the 1997 IEEE EMC Symposium paper on this site: A Method for Troubleshooting Noise Internal to an IC (~140K). In this method, a square loop is made so that one side of the loop spans the distance from the center to the edge of the chip package. The loop is rotated 360 degrees looking for maximum noise while one corner is held at the package center. The paper includes many details omitted here. Interpretation of two typical cases, Figures 2 and 3 below is presented in this article.

Figure 2 shows a pulse recorded from a package similar in appearance and size to the one shown in Figure 1. The impulse shown in Figure 2 was an isolated pulse with very low duty cycle. Notice the peak value of about 125 mV. If the coupling of the voltage drop in the package to the loop is 25% (a typical value) then the voltage drop in the package is about 500 mV! This is enough to be cause for concern and its effect on the signal integrity of the chip should be investigated as outlined in the paper referenced above. In general, the effects on signal integrity of a loop output of more than 50 mV should be investigated.

  Ldi/dt pulse from square loop
Figure 2.
Impulse Example

Since the loop output is Mdi/dt (where the di/dt is of the current flowing on the bonding wires and lead frame), the current waveform is proportional to the integral of Figure 2. The positive going pulse is the rising edge and the negative pulse is the falling edge. For a square wave, these two pulses will be separated. In the plot of Figure 2 though, they are adjacent. This means the current rises, in a little over a nanosecond, only to immediately fall with a slightly slower fall time. This is not likely a real signal but possibly the current pulse that occurs when a pull-up device overlaps in time with a pull-down device resulting in cross conduction between power and ground for a brief period. There are several other possibilities, such as conflict with another chip on a bus, that can result in such a current waveform.

Figure 3, by contrast, shows a continuous signal from the loop. The fundamental frequency is about 125 MHz, but the interesting part is the easily seen third harmonic of about 375 MHz. The shape of the wave is similar to that shown in the April 2002 Technical Tidbit on this site, "Printed Wiring Board Coupling to a Nearby Metal Plane." In that article, the oscillator output excited a board resonance at the third harmonic of the oscillator frequency. In the present case, a board feature that resonates at 375 MHz may be excited. An example might be a path crossing a ground plane break or a misterminated transmission line. Another possibility arises from circuitry and time delays internal to the device.

The difference between Figures 2 and 3 is that while the pulse in Figure 2 may be a signal integrity problem because of its amplitude, the wave in Figure 3 may be an EMC emissions problem because it is continuous with significant energy. Even though the peak amplitude is only about 13 mV, about one tenth the peak amplitude in Figure 2, the inductive voltage drop between the chip die and one or more leads exiting the package is likely to be about 50 mV. This could represent a noise plateau over the board ground plane driving all the leads of the chip with respect to the ground plane.

Considering that it only takes a couple of millivolts fed into an appropriate radiating structure to cause an emissions problem, every lead from this chip may be a potential EMC problem waiting to happen. Even an output that is pulled low to drive an LED continuously, has the capability of delivering significant energy to a radiating structure such as the board itself or connected cables.

Ldi/dt CW signal from square loop
Figure 3.
CW (Continuous Wave) Example

Conclusion: Useful information can be obtained from relatively simple measurement techniques. The data above clearly shows detection of possible signal integrity and EMC problems in a chip package by just looking at the output from a square loop held against the chip package.

References:

 The data in the waveforms above was taken with an Agilent Infinium 54845a oscilloscope.

There is much that can be said about the above data and this measurement technique that is not included here because of space limitations. More detailed information will be published on this topic and others in white papers on this website in the future. A demonstration of this effect has been recently added to my seminars.

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Copyright © 2003 Douglas C. Smith